| 摘要 |
PURPOSE:To make possible a bias test for wiring patterns in a board, which are not being connected to I/O pads, by a method wherein arbitrary ones of pads for bonding the I/O leads of a bare chip to correspond to a die pad on a circuit board are connected to the die pad through the cuttable wiring patterns. CONSTITUTION:As plural pieces of integrated circuit bare chips are mounted on a multilayer circuit board, bonding pads 1, a die pad 20 and groups of wiring patterns 21 are respectively formed at positions to be mounted with those chips. The wiring patterns 21 shall be patterns of a fine line width, which can be physically cut by a cutter and so on or can be fuse-cut with heat, chemical substances and so on. Through these wiring patterns 21, arbitrary ones of the bonding pads 1 and the die pad 20 being surrounded with those bonding pads 1 are electrically connected to each other. Thereby, a bias test can be conducted about a plurality of the wiring patterns easily, simultaneously and furthermore, without being subjected to restrictions on temperature.
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