| 摘要 |
PURPOSE:To omit a useless memory accesses by invalidating the contents shown by the store destination address of a store instruction when it is detected by means of said store destination address that this destination address is registered in a branch history table. CONSTITUTION:When the prefetch of an instruction is started, an address shown by an instruction counter 3 is selected by a selector 15 via a signal line 31 and sent to a memory control part (not shown here). At the same time the output of the counter 3 is selected by a selector 7 for retrieval of a branch history table 9. A comparator 10 detects that the address of an instruction word extracted out of the output of the counter 3 is registered in the table 9. At the same time, an AND gate 11 detects that the result of detection of the comparator 10 is valid based on the information on a valid bit flag corresponding to the output of the counter 3 and stored in the table 9. Then the result of detection of the gate 11 is informed to a control part 12.
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