发明名称 PLL OSCILLATING CIRCUIT
摘要 PURPOSE:To eliminate an expensive electromagnetic delay line, and to form a semicon ductor integrated circuit by changing temporarily a frequency division ratio of the first frequency dividing means for frequency dividing a reference frequency signal, and changing a phase of an output of an oscillating circuit. CONSTITUTION:When a frequency division ratio control signal 3 is in a low level, a steady operation is executed, and in an output 7 of a voltage control oscillating circuit 6, a signal which becomes an oscillation frequency f0=2/3fr is obtained. Also, when the frequency division ratio control signal 3 is set to a high level for the time of a four-wave portion of a reference frequency fr, a 1/3 and 1/4 frequency dividing circuit 2 executes a 1/4 frequency dividing operation only during this time, and outputs a signal which is delayed by one wave portion of the reference frequency fr. It corresponds to a fact that the phase is delayed by a 2/3 wave portion of the oscillation frequency f0. Also, when the frequency division ratio control signal 3 is set to a high level once, the phase is delayed by a 4/3 portion to which a 2/3 wave portion of the oscillation frequency f0 is added, namely, a 1/3 wave portion of the f0. In such a way, the phase can be delayed without using an electromagnetic delay line, therefore, this circuit becomes inexpensive, and also, it can be converted to a semiconductor integrat ed circuit.
申请公布号 JPS63187917(A) 申请公布日期 1988.08.03
申请号 JP19870020905 申请日期 1987.01.30
申请人 NEC CORP 发明人 OGAWA ATSUSHI
分类号 H03L7/18 主分类号 H03L7/18
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