| 摘要 |
PURPOSE:To shorten the processing time in a memory access controller by reading out a data from a data part of a cache memory in parallel with an index of an address registering part of the cache memory when the preceding memory access request and a memory read-out request executing an access to the same level of a cache. CONSTITUTION:When a memory access request does not exist in a stage 3, and also, memory access requests of a stage 2 and a stage 1 are not issued by the same CPU, an output of a level holding register 109 holding a cache hit level of the preceding memory access request is compared with and a cache hit level of the memory access request of the stage 1. If they are equal, the memory access request of the stage 1 executes read-out of a data of a cache memory 10C simultaneously in parallel with an index of a cache memory address registering part 104, and stores a read-out data in a cache data register 10D by the next clock timing. In such a way, the processing time in a memory access controller can be shortened.
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