| 摘要 |
PURPOSE:To realize high speed operation by connecting each source terminal of a P-channel MOS transistor (TR) and an N-channel MOS TR in common to an output terminal of a complementary MOS inverter and connecting each gate terminal of both the MOS TRs in common. CONSTITUTION:Each circuit structure comprising P-channel MOS TRs Q3, Q4 and N-channel MOS TRs Q5, Q6 connected in series by stage is connected by using sources of the P-channel MOS TR Q3 and the N-channel MOS TR Q5 in common, a drain of the P-channel MOS TR Q4 is connected to a ground terminal VSS and the drain of the N-channel MOS TR Q6 is connected to a power terminal VDD. The switching of an inverter S1 is started when the level of an input terminal N1 is VDD/2 and since the output terminal N2 is clamped at the intermediate potential through the switching, the circuit is operated earlier than the output of a conventional circuit by the time change from the ground or power potential to the clamp potential.
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