| 摘要 |
PURPOSE:To decrease the sampling period equivalently by using a linear approximation so as to increase number of sample points to a multiple of the power of 2. CONSTITUTION:A sample strings of samples Xn, Xn-1 having a time difference DELTAt of one clock signal at an optional clock time tn is inputted to input terminals 1, 2 of a basic block a1 and the samples Xn, Xn-1 are added by an adder 3 to form a sample yn(1) via a one-bit right shifter 4 applying the arithmetic operation of yn(1)=(Xn+Xn-1)/2. It is used as a sample string and fed to an input terminal 5 of an output selection switch b1, a sample Xn is inputted to other input terminal 6 to generate a sample string of ...yn(1), Xn, yn+1(1), Xn+1... at an output terminal 7 of the selector switch b1 at a clock period being a half of the time difference DELTAt of the input sampling clock signal. Thus, the sample interval is interpolated by the direct approximation to reduce the clock period.
|
