发明名称 BUFFER CONTROL CIRCUIT
摘要 PURPOSE:To efficiently use a buffer memory by dividing a buffer into plural memory blocks and using memory blocks in series or in parallel in accordance with the data volume. CONSTITUTION:A buffer memory 3 in which data of an input/output device is temporarily stored is divided into plural blocks #1-#n, and an address management control means 1 which designates the upper address of the divided buffer and an address counter 2 which designates the lower address are provided. Since divided blocks of the buffer are used in series or in parallel in accordance with the data volume, the buffer is efficiently used.
申请公布号 JPS63231618(A) 申请公布日期 1988.09.27
申请号 JP19870066086 申请日期 1987.03.20
申请人 FUJITSU LTD 发明人 AIZAWA RYOICHI
分类号 G06F3/06;G06F5/06 主分类号 G06F3/06
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