发明名称 E/EMOS CIRCUIT
摘要 PURPOSE:Not to transmit the fluctuation of a power source/GND as a noise to an output terminal by inserting a diode between the output terminal of E/E (enhancement/enhancement) MOS circuit and lower side N channel MOS transistor. CONSTITUTION:When a high level voltage is given to an input terminal 3, the upper side N channel MOS transistor(NMOS)1-1 of the E/EMOS circuit is turned off and the lower side N MOS1-2 is turned on and the noise is prevented from being transmitted to the output terminal 4 by the clamp characteristic of the diode 5 when a GNDVSS fluctuates in this state. On the contrary, if a low level voltage is given to the input terminal 3, the MOS1-1 is turned on and the MOS 1-2 is turned off and the noise is not transmitted to the output terminal 4 because the gate potential of the MOS 1-1 lowers so as to cut off when the power source VDD fluctuates in this state. Even if either VDD or the VSS fluctuates, the noise is not transmitted to the still output terminal 4, so that a malfunction does not occur in the integrated circuit of a reception side.
申请公布号 JPS63232519(A) 申请公布日期 1988.09.28
申请号 JP19870063744 申请日期 1987.03.20
申请人 HITACHI LTD 发明人 TAMURA SHIGEAKI
分类号 H03K19/0948;H03K17/16;H03K17/687;H03K19/003;H03K19/094 主分类号 H03K19/0948
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