| 摘要 |
PURPOSE:To enable evaluation of performance per test unit, by providing a switch at the front stage of a test unit for testing by a scan design to control a clock of a latch circuit so arranged to be a shift register. CONSTITUTION:To apply an input signal for testing of a test units 11 into which a logic circuit is divided, input side latch circuits 60a and 60b so arranged to be a shift register are provided on the input side of the test units 11 while output side latch circuits 61a and 61b are provided on the output side of the test units 11 to receive response output of the test units 11 to be compared with an expected value. Switches 12a and 12b are provided between the test units 11 to be compared with an expected value. Switches 12a and 12b are provided between the test units 11 and the latch circuits 60a and 60b separately to simultaneously input multiple bits of output signals from corresponding latch circuits 60a and 60b into multiple bits of input of individual test units 11. Then, clocks of latch circuits 61a and 61b are controlled with the switch 12a and 12b to prevent accidental inflow of data into the test units 11 thereby enabling evaluation of performance per test unit.
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