| 摘要 |
PURPOSE:To facilitate the high speed operation of a Bi-CMOS-LSI by a method wherein the base resistance value of an N-P-N bipolar transistor is reduced when the Bi-CMOS-LSI is manufactured. CONSTITUTION:A photoresist layer 20 is applied while a photoresist layer 18 is left on an emitter polycrystalline silicon layer 19 and ordinary alignment, exposure of a mask pattern and development are carried out. Then ions of, for instance, boron are implanted with the photoresist layers 18 and 20 as a mask. By this process, the low resistance P<+> layer 12 of an N-P-N bipolar transistor is formed in a manner of self-alignment with the emitter polycrystalline silicon layer 19. Then the emitter and collector electrode parts of the N-P-N bipolar transistor and the source and drain parts of an N-type channel MOS-FET are simultaneously exposed with a photoresist layer 21 as an ion implantation mask and, after that, a heat treatment is carried out, a CVD oxide film is deposited, contact holes are drilled and aluminum wirings are applied to complete a Bi-CMOS-LSI. |
