| 摘要 |
PURPOSE:To reduce base-collector parasitic junction capacitance by selectively forming a semi-insulating layer consisting of an intrinsic semiconductor material lattice-matched with a collector layer and a base layer between the collector layer and the base layer. CONSTITUTION:An N-type collector layer 2 is shaped onto a semi-insulating semiconductor substrate 1, and a semi-insulating layer 4 composed of an intrinsic semiconductor layer lattice-matched with the collector layer 2 and a base layer 5 is formed selectively onto the surface of the layer 2. The P-type base layer 5 is shaped onto an active region in the layer 2 and the layer 4, and an N-type emitter layer 6 is formed onto at least the active region in the layer 5. Collector, base and emitter electrodes 7c, 7b and 7e are shaped onto exposed surfaces of the layer 2, the layer 5 and the layer 6 respectively. Accordingly, base- collector parasitic junction capacitance is reduced.
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