| 摘要 |
PURPOSE:To eliminate unnecessary activation of memory cell and sense amplifier so as to reduce the power consumption of a semiconductor storage device, by activating the memory cell and sense amplifier of partial rows which are determined in accordance with the row address of a memory cell to be accessed at the time of ordinary accessing time. CONSTITUTION:A line address RA for ordinary access is given to a line decoder 3 and a signal corresponding to a row address is given to a row decoder 4 based on the discrimination made by an arbiter circuit. When a group containing the row, to which a memory cell (for example, M13) to be accessed belongs, is specified and only the section related to the row containing the memory cell M13 is electrically connected to the row decoder 4, the decoder 4 is activated and the main word line WLM1 of the line decoder 3 is driven. The potential change of the main word line WLM1 is transmitted to an auxiliary word line WLS12 and gates of the cell M13 and M14 are opened. The stored data are extracted as potential differences of bit line pairs BL3a, BL3b and BL4a, BL4b. Moreover, when activating signals are given to a sense amplifier activating signal line 25, the signals are detected and amplified by sense amplifiers SA3 and SA4.
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