| 摘要 |
PURPOSE:To improve performance based on rapid access by selecting and transferring corresponding data when a processor outputs a memory reading request during nibble operation and data transferring to a cache memory. CONSTITUTION:The title system is provided with a transfer control means 40 for transferring data to be transferred in the 1st time out of data to be transferred 4 times by nibbling operation at the time of detecting a cache mishit to a processor 10, selecting corresponding data 51 out of data to be transferred in the 2nd time and after and transferring the selected data 51. Namely, a device having a 32-bit processor and a 16-bit main memory transfers 1st and 2nd transfer data continuously to the processor 10. When the processor and the main memory have the same bit width, the 2nd address data and after out of transfer data are compared with address data outputted based on a memory reading signal and data outputted at the time of coincidence of data are transferred. Consequently, system performance due to rapid access can be obtained.
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