发明名称 GATE ARRAY SEMICONDUCTOR DEVICE
摘要 PURPOSE:To effectively utilize bonding pads and external cells by a method wherein an interval between the bonding pads formed at the outer circumference of a substrate is made wide with reference to a space between external cell rows formed at the inside of the pads. CONSTITUTION:The following are formed on a semiconductor substrate: an internal cell region 4; external cell rows 2 formed at the circumference of the internal cell region 4; bonding pads 3 formed at the circumference of the external cell rows 2. In this gate array semiconductor device, an interval between the bonding pads 3 formed at the external circumference of the substrate is made wide with reference to a space between the external cell rows 2 formed at the inside of the pads 3. Furthermore, bonding pads corresponding to external cells at both ends of the external cell rows 2 are formed at the outside from both ends of the external cell rows 2. By this setup, the external cells can correspond to the bonding pads 3 freely; it is possible to effectively utilize the bonding pads 3 at corners and the unused external cells.
申请公布号 JPS63250144(A) 申请公布日期 1988.10.18
申请号 JP19870085951 申请日期 1987.04.07
申请人 NEC CORP 发明人 KOBAYASHI TAKESHI
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
主权项
地址