SEMICONDUCTOR MEMORY DEVICE CONTAINING MOS BIPOLAR COMPOSITE MULTIPLEXER CIRCUIT

摘要

PURPOSE:To increase a memory reading speed by using a bipolar transistor to drive plural common data lines. CONSTITUTION:In a bit line selecting circuit 5, a control signal obtained by the AND of a block selecting signal and a column selecting signal is set at 'L' for a selected column of a selected block. Then a MOSFET having a large gm conducts and a bit line is pulled up by VCC. The information on a memory cell of the line designated by a word line is produced on a bit line and supplied to the bases of bipolar transistors TRQ1 and Q2 of a data line driving circuit 6. Then the information on the bit line is produced on a 1st common data line. The 1st common data line of each block is supplied to the bases of bipolar TRQ3 and Q4 whose emitters are connected to the 2nd common data line via a data line driving circuit 7. Then the information on the 1st common data line is produced on the 2nd common data line.