发明名称 NULLIFICATION SYSTEM FOR ADDRESS TRANSLATION BUFFER
摘要 PURPOSE:To reduce an overhead, required for the nullification process of a TLB by nullifying selectively only an address translation buffer (TLB) entry, which is necessitated to be nullified, and suppressing the nullification of the entry, which is not necessitated to be nullified. CONSTITUTION:When a TLB nullification request is informed from an execution unit through a line L12, the interruptions of an instruction fetch and an instruction execution are requested through L13, and the completion of them is waited. When the completion of the interruption of the instruction execution is informed through L23, a TLB nullification start request is sent to a TLB control part 505 through L14. The control part 505 nullifies selectively only the entry, corresponding to a virtual machine identification information, which has issued a purge PTLB instruction according to an information from a virtual machine identification information control register 501. The TLB nullification completion of its own is transmitted through L16, and the nullification completion from other processor is transmitted through L22. When the TLB nullification processing of all processors is completed, the restart of the instruction execution is informed through L18 to itself, and through L19 to other processors.
申请公布号 JPS63286944(A) 申请公布日期 1988.11.24
申请号 JP19870121253 申请日期 1987.05.20
申请人 HITACHI LTD 发明人 YOSHIOKA SHIYOUICHIROU;UMENO HIDENORI
分类号 G06F12/10 主分类号 G06F12/10
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