| 摘要 |
PURPOSE:To obtain a decoded output with a steep rise by providing a latch circuit and an output buffer circuit to prevent a delay time generated by an AND gate from influencing the decoded output. CONSTITUTION:A latch circuit 31 keeping a signal generated by an AND gate section (comprising n-MOS transistors (TRs) 21-24) till a clock of logic '1' comes again when the clock input signal is logical '1', is connected to an output stage of the AND gate section to output logical '1' only when both the clock input and the output of the latch circuit 31 are logical '0'. An output buffer circuit 35 is connected to an output stage of the latch circuit 31. Thus, the latch circuit 31 keeps the signal to prevent a time delay caused by the AND gate section from being delivered to a decode output signal, and a decode signal is supplied immediately after the clock signal is switched by the output buffer circuit 35, then the decoded output signal with steep rise is obtained.
|
