发明名称 |
Multi-processor using shared buses |
摘要 |
A multi-processor apparatus is disclosed which includes an array of separately addressable memory units and an array of separately addressable processors. A first unidirectional bus delivers data from a selected processor to a selected memory unit. A second unidirectional data bus delivers data from a selected memory unit to a selected processor. Arbitor circuits control the flow of data to these data buses.
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申请公布号 |
US4803617(A) |
申请公布日期 |
1989.02.07 |
申请号 |
US19880166756 |
申请日期 |
1988.03.03 |
申请人 |
EASTMAN KODAK COMPANY |
发明人 |
BERARDUCCI, THOMAS N. |
分类号 |
G06F13/18;G06F13/364;G06T1/20;(IPC1-7):G06F13/40;G06F13/14;G06F15/16 |
主分类号 |
G06F13/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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