DIGITAL TIMESLOT AND SIGNALING BUS IN A DIGITAL PBX SWTICH

摘要

Several line card modules (12A-D) are interconnected by a nearly universal parallel bus (10), and are associated with a number of clock signals, preferably operating at the same frequency but with a set phase displacement. The line card modules may thereby communicate during predetermined portions of a timeslot and more than one may communiate during a timeslot. Pref. a frame of timeslots is set up with each module associated a set of timeslots in each frame and a unique signal to each timeslot allows that allocated to a particular module module to communicate with that timeslot.