发明名称 CLOCK SIGNAL GENERATION CIRCUIT
摘要 The clock signal generating circuit includes a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line. A second N-channel transistor is connected between a common connection point of the P-channel transistor and thr first N-channel transistor through a node, and a clock signal is applied to a gate of the second N-channel transistor. A capacitor is connected between the gate of the first N-channel transistor and a gate of the P- channel transistor. A bootstrap capacitor is connected to the common connection point.
申请公布号 KR900001807(B1) 申请公布日期 1990.03.24
申请号 KR19870000960 申请日期 1987.02.06
申请人 FUJITSU CO.LTD. 发明人 DAKEMAE YOSHIHIRO
分类号 H03K5/02;H03K17/04;H03K19/017;(IPC1-7):H03K5/135 主分类号 H03K5/02
代理机构 代理人
主权项
地址