| 摘要 |
The circuit is for utilizing a high voltage clock signal and also reducing the area of a capacitor whose voltage at one terminal is boosted by the output of the first driver by further raising a high voltage outputted by the capacitor. The potential at one terminal of the capacitor (C) is raised by the output of the first driver (D) to generate the high voltage, which is sent out to an output terminal through the second driver (D2), and a transistor (TR1) for charge supply is interposed between the output terminal and a power line.
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