| 摘要 |
An input voltage level control unit converts a transistortransistor- logic drive level to a metal-oxide-semiconductor drive level during transmission of an address strobe signal. An address buffer control unit generates an address signal and an inverted address signal in response to a trailing edge of the address strobe signal. a clock signal generating unit generates a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and a further unit inhibits a drive of the word line by the clock signal when the address strobe signal is at high level in the timing of a leading edge of the clock signal.
|
