| 摘要 |
The EPROM device has a number of memory cell FETs arranged in a matrix on a semiconductor substrate. The memory cell FET has a floating gate for storing voltage on it and controlling the conductivity of the memory cell FET, and a gate insulation film provided between the floating gate and the substrate for insulating the floating gate from the substrate. A control gate positioned over the floating gate controls the voltage of the floating gate. Device separation regions provided on both sides in gate width direction of the floating gate separate the memory cell FET from adjacent memory cell FETs on both sides.
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