SEMICONDUCTOR MEMORY DEVICE

摘要

The memory includes a cell array constituted by at least a pair of memory groups. A bit line pair is coupled to a memory group and a second bit line pair is coupled to a second memory group. A sense amplifier is coupled to the first memory group for sensing and amplifying a potential difference in the first bit line pair. The sense amplifier comprises P-channel transistors. A second sense amplifier is coupled to the second memory group for sensing and amplifying a potential difference in the second bit line pair. The second sense amplifier comprises N-channel transistors. The first and second sense amplifiers are driven with mutually opposite phases.