| 摘要 |
A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (26) for multiplying the input signal with a local oscillator signal (LOa-LOd) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, operates in a SEARCH mode to supply acquisition reference signals (1xi, 1xq, 2xi, 2xq) to the multipliers (36). The resulting integrated values (Ia-Id) are proportional to the sine and cosine of the pahse ( phi ) of the input signal. The polarities (Sa-Sd) of these integrated values (Ia-Id) are processed to estimate this phase ( phi ) and to generate a reset signal (RESYNC) for the receiver (22) at the appropriate time.
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