| 摘要 |
arraying NMOS transistors so as to select or not to select each bit line by using the selecting transistor to array the bit lines; connecting the source of the selecting transistor to the 32 cells serially; and connecting word lines to the gates of the cells. The method uses a 8 bit data address disgnating method arrayed by the 32 word lines, the 8 bit lines, one selecting transistor and the eliminated cell, permits high density array, and eliminates the parasitic capacitance between the buried N+ region and the substrate.
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