| 发明名称 |
Dual memory timing system for VLSI test systems |
| 摘要 |
A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.
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| 申请公布号 |
US5028878(A) |
申请公布日期 |
1991.07.02 |
| 申请号 |
US19890435127 |
申请日期 |
1989.11.13 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
CARLSON, MARK E.;MYDILL, MARC R. |
| 分类号 |
G01R31/28;G01R31/319;G06F11/22 |
主分类号 |
G01R31/28 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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