| 摘要 |
DRAM cell field architecture having higher-ranking bit switch lines and higher-ranking bit lines. The DRAM cell field architecture has a bit line pair (BLj, BLj+2) which is respectively selected from a plurality of bit line pairs by bit switches (5 through 12) in every individual memory block. Of the respectively selected bit line pairs, only the bit line pairs of the selected memory block in each memory block are in turn through-connected to the higher-ranking bit lines (IOk through IOk+3). The higher-ranking bit lines can thereby proceed in a single, for example the second, metallization level in common with higher-ranking bit switch lines (CSLk through CSLk+3) that drive the bit switches, this metallization plane being better utilized as a result thereof. Depending on the required degree of parallelization, evaluators can be eliminated as a result of the higher-ranking bit lines, whereby the advantage of a short access time given moderate power consumption is preserved for individual access.
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