| 摘要 |
A phase locked loop (PLL) frequency synthesizer capable of switching the output frequency thereof at high speed. The frequency synthesizer has a second phase/frequency comparator and a second variable frequency divider in addition to a first phase/frequency comparator which is included in a PLL. The synthesizer switches over the time constant of a loop filter by the output of the second phase/frequency comparator, i. e., independently of the PLL which is responsive to the output of the first phase/frequency comparator. As a result, the time constant of the loop filter is switched over at an advanced timing to thereby reduce PLL tuning time.
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