| 摘要 |
A floating-point multiplication apparatus is described which includes circuits for predicting the logical sum of a set of low-significance bits which are truncated from an intermediate product resulting from multiplying together two mantissas, without the necessity for examining the truncated bits, to thereby determine the state of a bit which is attached to replace the truncated bits in the intermediate product and upon whose state a subsequent rounding-off operation depends. A floating-point addition and subtraction apparatus is also described in which numbers of trailing zeros of the mantissas of two operands are derived concurrently with determining which of the operands has a smaller value of exponent, with the result of that determination being used to select the appropriate number of trailing zeros, for use in setting the state of a bit on which a subsequent rounding-off operation depends.
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