| 摘要 |
<p>PURPOSE:To quicken the descramble processing by adding a synchronization pattern position signal outputted from a 2nd counter means on the occurrence of an asynchronization state to a synchronization pattern position signal outputted by a 1st counter means. CONSTITUTION:A counter circuit 6 being a 2nd counter means is configured the same as a counter circuit 4 being a 1st counter means and reset by a SYD signal being a synchronization pattern detection signal fed from a SYNC pattern detection circuit 1 and made synchronous with the SYD signal. When count of LRCK signals reaches 588, an SRPS2 signal being a 2nd synchronization pattern position section is generated. When an NGS signal is at a low level which represents the synchronization state, the passing of the SRPS2 signal through an AND gate G6 is inhibited. When the NGS signal is at a low level which represents the asynchronization state, the SRPS2 signal is fed to an OR gate G7. Upon the receipt of either the SRPS1 signal or the SRPS2 signal, the OR gate G7 an SRPS3 signal to a linear shift register circuit 3.</p> |
