INTEGRATED CIRCUIT AND GATE ARRAY MASTER CHIP

摘要

PURPOSE:To make it possible to control for the optimum fanout, reducing an integrated circuit layout area. CONSTITUTION:There are provided fanout control cells 10 together with general cells 20. The general cells 10 and the fanout control cells 20 are identical in their logic circuits, but only differ from their delay time. More specifically, it is possible to control for the optimum fanout by installing these general cells 20 and the fanout control cells 10 to a library or a gate array master chip which is under the array structure of several basic cells at least in an internal logic circuit region.