| 摘要 |
<p>PURPOSE:To prevent cycle expansion of output signal of a pattern memory by inserting pulses locally in a clock which makes an address counter progress stepwise. CONSTITUTION:Along with stepwise progress of an address counter 14, signals A0 and B0 are read out and fed to an insertion position detecting circuit 12, and thereafter detection result is output in a manner that 24 of a signal line 23 holds one clock cycle. Then, signal of a signal line 27 is added to the address counter 14, and, since detection of pulse information delays by one clock when content of a pattern 11 is read out to output signal, signals Aa and Ba obtained from the output signals A0 and B0 through timing by starting-up clock of the signal line 27, are the very signals to be obtained. When a standard clock cycle is T, an event interval of the signal Aa stays as it was, and is not expanded even though an event of signal B' exists between events of the signal Aa.</p> |
