发明名称 PERSONAL COMPUTER
摘要 <p>PURPOSE:To lower the clock frequency of a CPU and to reduce the power consumption of the CPU by providing a circuit stopping the clock input of the CPU only when the weight is assigned to the CPU in an arbitrary bus cycle. CONSTITUTION:The personal computer consists of a decoder 1, a ready control circuit 2 inputting the control signal of weight numbers to be outputted from the decoder 1 and a basic clock 6 and generating a CPU clock control signal 5 and a ready signal for the CPU, and an AND gate 7 stopping the output of the CPU clock 5 during the weight period of the bus cycle based on the CPU clock control signal of the ready control circuit 2.</p>
申请公布号 JPH0588774(A) 申请公布日期 1993.04.09
申请号 JP19910252126 申请日期 1991.09.30
申请人 TOSHIBA CORP 发明人 ISHIKAWA KENICHI
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
主权项
地址