| 摘要 |
The circuit for reducing the number of transistors to reduce layout size comprises first inverter (I1) for inverting a second clock signal, a first NMOS TR (N1) for receiving an input signal (Vi) by using the second clock signal as a gate driving voltage, a first PMOS TR (P1) for receiving the input signal (Vi) by using an output of the inverter (I1) as a gate driving voltage, a second inverter (I2), a fourth inverter (I4) for inverting a first clock signal, a first clock inverter (CI1) for inverting the inverter (I2) output by using the first clock signal as a sync. signal, a second PMOS (P2), a third PMOS (P3), a fourth PMOS (P4), a second NMOS (N2), a third NMOS (N3), a fourth NMOS (N4), a third inverter (I3), a second clock inverter (CI2) and a clock NAND gate (CA) for receiving the second and third inverter (I2,I3) outputs to output a final output signal (V).
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