| 摘要 |
The digital chip has an input bus (eb) for the clocked input data (de), which is synchronised within the chip with a clock signal (t) having a frequency which is a whole multiple of the input data clock frequency. The clock signal (t) is fed to a frequency divider (ft) providing one of a number of possible rectangular output signals with differing pulse pause ratios for each data line of the input bus (eb). A measuring circuit (ms) compares the phase of the clock signal (t) with the input data clock, to provide an output signal for a data synchroniser (d1), in turn providing an output signal for the reset input (rs) of the frequency divider (ft). This provides the rectangular output signal with a pulse duration lying centrally between 2 successive data transition points of the synchronised input data.
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