Multi-port memory e.g. for register file in microprocessor - has several access devices for individual cells and simultaneous access blocking

摘要

The memory cell field (1a) includes a number of two-port memory cells (MC1). There is a first line address decoder (21) for a first address signal (A1) for selecting a first word line (WL), contained in numerous word line groups. A second line address decoder (22) for a second address signal (A2) selects a second word line. The second word line is also contained in a number of such word lines. A word line driver circuit (3a) receives the output signals of the two line address decoders to drive the two word liner (WL1,2) in agreement with a preset blocking condition. ADVANTAGE - Has facility for numerous simultaneous access to same memory cell with increased speed.