| 摘要 |
<p>PURPOSE:To prepare a signal delayed for a fixed time for the control output of a binary control. CONSTITUTION:The signal delay circuit is provided with a circuit shown by dotted line parts 1 and 2 detecting the rise and fall of an original signal, respectively, holding the rise and resetting itself after a prescribed delayed time passes and a circuit shown by dotted line parts 3 and 4 operating in the same way as the parts 1 and 2 on the condition that the above mentioned circuit is holding and operating. A signal delayed for the original signal is prepared by imparting the OR signal of the rise of the dotted line parts 1 and 3 or the signal synchronized with this as the set signal of a SR-FF circuit 11 and imparting the OR signal of the signal synchronized with this as the reset signal of the SR-FF circuit 11 in the fall of the dotted line parts 2 and 4.</p> |
