Digital signal processor using counter(s) and frequency divider(s) - connected in chain circuit, as shift resistor, forming clock flip-flop

摘要

The counters and/or frequency divider (6) form a combination with signal processors for analog signals (3). The counter and/or frequency divider circuits contain simultaneously clocked flip-flops (11-16) in a chain circuit as a shift register. The counters and frequency dividers are pref. grouped with at least one circuit for processing the analog signals in an integrated structure (1). At least one output signal of one selected flip-flop may be supplied to an input of the first flip-flop of the chain circuit. In a logic circuit the selected flip-flop output signals are typically linked together for affecting an input signal for the chain circuit flip-flop. USE/ADVANTAGE - For digital signal control of analog signal processor, with reduction of counter and frequency divider interference to analog video signals.