发明名称 VARIABLE LENGTH ENCODING AND DECODING CIRCUIT
摘要 <p>PURPOSE:To reduce the memory circuit required for a parallel processing by performing a parallel processing by a picture element unit in the variable length encoding and decoding circuit in the encoding of a TV signal. CONSTITUTION:Inputted picture data is distributed to variable length encoders 4 to 7 by a picture element unit in a separation circuit 3 and a variable length encoding processing is performed for the data by a parallel processing. After encoded data is written in memory circuits 8 to 11, each encoded data is multiplexed by a word unit in a multiplex circuit 12. At the time, the number of word of each encoded data to be outputted from the variable length encoders 4 to 7 is also multiplexed with the encoded data so as to normally separate the data at the time of decoding even if the data are multiplexed by a word unit.</p>
申请公布号 JPH05300486(A) 申请公布日期 1993.11.12
申请号 JP19920099244 申请日期 1992.04.20
申请人 NEC CORP 发明人 OKAJIMA MASAYUKI
分类号 H04N19/00;H04N19/423;H04N19/426;H04N19/436;H04N19/91;(IPC1-7):H04N7/13 主分类号 H04N19/00
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