| 摘要 |
PURPOSE: To manufacture each element on the surface of one semiconductor chip. CONSTITUTION: This circuit is manufactured by including an n<-> and p<-> channel low voltage field effect logical transistors 403, n<-> and p<-> channel high voltage insulating gate field effect transistor 405 related with an EEPROM memory array or the gate control of this similar one, n<-> and p<-> channel drain extension insulating gate field effect transistor 407, vertical and horizontal annular DMOS transistor 409, Schottky diode 411, and FAMOS EPROM cell 412. Also, a high reliable 'non-superimposed' double level poly-EEPROM cell is developed. |
