发明名称 SYNCHRONIZING STEP-OUT DETECTING CIRCUIT FOR PHASE LOCKED LOOP
摘要 PURPOSE:To improve the detection accuracy, to eliminate the delay of the detection time by discriminating as non-synchronizing between a subordinating synchronizing clock and a subordinated synchronizing clock when the pulse width becomes larger than a imported threshold value. CONSTITUTION:An input signal 108 of a subordinated synchronizing clock and an output signal 113 of a voltage control oscillator 104 being a subordinating synchronizing clock are inputted to a phase comparator 101. When the phase of the input signal 108 leads, the pulse width of an INC pulse signal 109 becomes longer. When the phase of the input signal 108 lags, the pulse width of a DEC pulse signal 110 becomes longer. Accordingly, the non-synchronizing can be detected by monitoring the pulse width. First, a pulse width monitoring section 106 uses a detection reference clock to monitor and measure the pulse width. Then a non-synchronizing detecting section 107 discriminates monitoring result 116 of the pulse width monitoring section according to the sensitivity imparted by a detection sensitivity cutting signal 115 and outputs a non-synchronizing signal 117 when judged to be non-synchronizing.
申请公布号 JPH05327488(A) 申请公布日期 1993.12.10
申请号 JP19920126446 申请日期 1992.05.19
申请人 HITACHI LTD;HITACHI GAZOU JOHO SYST:KK 发明人 SAIKI EISAKU;TATEYAMA TSUYOSHI;SUZUMURA SHINTARO;NAGATA SHUNJI;URAGAMI KEN;MIYAZAWA SHOICHI
分类号 G11B20/14;H03L7/095 主分类号 G11B20/14
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