| 摘要 |
PURPOSE:To prevent a sudden change of an effective power by a method wherein a speed deviation is made zero substantially for following by adding a certain bias signal to a speed target signal before parallel and the bias signal is made zero little by little after the parallel. CONSTITUTION:A speed instruction signal Na outputted by a speed instruction preparing part 15 and a speed signal N undergo transition in a state of being in accord substantially with each other, from a time t1. The speed instruction signal Na is outputted to an adder-subtracter and added up to the speed signal N, a deviation signal thereof becomes zero substantially, and the condition of parallel its established at a time t2. In this case, a signal obtained by addition of a bias signal B and a value of zero of a fixed value setting unit 19 is inputted to an integrator 16, an output of the integrator 16 attenuates from the value of the bias signal B before the parallel to the value of zero by a prescribed time constant of linear delay and the bias signal B becomes zero at a time t4. According to this constitution, the speed instruction signal is prevented from changing stepwise after the parallel. |
