FET mfg. process esp. with sub-micron quantum wire channel - using two-level electron beam resist system, with different electron exposure sensitivities in resist layers, and forming gate recess in gallium arsenide layer with holes dry etched in aluminium gallium arsenide channel layer

摘要

The FET mfr. involves depositing two electron beam sensitive resist material layers (S1,S2) on a semiconductor material film, with the upper layer (2) of lower electro-sensitivity than the first layer (1). An electron beam irradiates the first layer along a band (B1) at a set electron exposure dose, without irradiating the second layer, and a higher density electron irradiation exposure is applied to the second layer in sections (T1,T2) of the band. The resin layers are developed to remove the exposed sections. The semiconductor material layer e.g. GaAs in the band is chemically etched and reactive ion etching used to from holes in the semiconductor material (T1,T2) e.g. AlGaAs, forming aligned narrow connecting quantum wire in the transistor channel. USE/ADVANTAGE - Multiple channel, single dimension electron FET; mfr. of FET at mm frequency, with low noise factor. Self-aligned gate metal deposition; reduced parasitics in transistor.