Signal handling system with a shared data memory

摘要

A signal processing system includes a superior control processor (2) and a number of digital signal processors (4-10), which are controlled by the control processor and normally operate internally with real time applications. A shared data memory (18) is included with a bus (20), on which the control processor normally is bus master, and to which the signal processors have access. An arbitration logic (28) controls the access of the processors (4-10) to the shared data memory. The signal processors (4-10) are directly connected to the bus (20) and normally keep their data and address buses (22) on a high impedance level with respect thereto.