Wafer Level Packaging of Electronic Devices

摘要

Aspects of the invention are directed to an electronic device package including an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

主权项

1. A wafer level packaging of semiconductor devices comprising of:
a semiconductor device with a top face and bottom face and at least one metal pad located on bottom face and; a top cover layer affixed to top face of semiconductor device and; a bottom cover wafer affixed to bottom face of semiconductor device; wherein the bottom cover wafer has at least one via extending from external face of bottom wafer to internal face of said bottom wafer; and an electroplated metal layer extends from the external face of bottom wafer through the via to the metal pad.