Device Isolator with Reduced Parasitic Capacitance

摘要

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

主权项

1. An isolator structure in an integrated circuit formed at a semiconducting surface of a substrate, comprising:
a first buried doped layer of a first conductivity type disposed within a substrate of a second conductivity type, the first buried doped layer having an upper surface beneath the surface; a first tank region of the second conductivity type overlying a portion of the first buried doped layer; a first well region of the first conductivity type disposed at the surface of the substrate and overlying a portion of the first tank region; a first boundary doped region of the first conductivity type disposed at the surface and laterally surrounding the first tank region, the first boundary doped region extending into the surface and contacting the first buried doped layer; a first conductor element disposed near the surface at a location overlying the first well region, separated therefrom by dielectric material; and a second conductor element disposed near the surface at a location overlying the first conductor element, separated therefrom by dielectric material.