| 摘要 |
<p>PURPOSE: To interleave data transfer for each slice by dividing the data transfer into the sequence of plural data slices by each channel. CONSTITUTION: The circuit architecture of plural interleave operating DMA channels is provided with a dual port memory, channel sequencer, and channel interleave control part. The dual port memory stores the slices of data to be transferred through the channels. The channel sequencer maintains the channel sequencing of the data slices in the dual port memory. The channel interleave controller allows the channels to interleave the data transfer by monitoring the channel interleave size, present data transfer count, and total transfer count. When a first channel reaches the channel interleave size, or when the first channel ends the transfer of the requested total transfer count, a second channel is allowed to transfer the data through the same medium as the first channel.</p> |
