| 摘要 |
In the present invention, a first and a second conductor pattern are disposed in a wiring substrate, and a wiring pattern is provided on the surface of the wiring substrate. A pair of lands are disposed so as to flank the wiring pattern. A first via connects the wiring pattern to the first conductor pattern and a second via connects the land to the second conductor pattern. A chip three-terminal capacitor has a long, flat shape in which the length dimension is greater than the width dimension. A first terminal is provided to both lengthwise ends of the chip three-terminal capacitor, and a second terminal is provided to both widthwise ends of the chip three-terminal capacitor. The chip three-terminal capacitor is mounted on the wiring substrate in such an orientation that the length direction of the chip three-terminal capacitor is oriented along the wiring pattern. The first terminals are connected to the wiring pattern and the second terminals are connected to the lands. The first via is disposed at a position where the chip three-terminal capacitor is overlapped. |
