| 摘要 |
The structure includes a silicon substrate (29), a gate electrode (11) formed on the substrate (29) in the curved form, a gate insulating layer (28) formed on the substrate, a semiconductor layer formed at the active region on the gate insulating layer (28), source and drain regions (13)(14) formed on the layer (28) at the place of the semiconductor layer and at the two sides of the gate electrode. A source offset region (31) is formed at the place of the semiconductor layer between the gate electrode and source region. The structure reduces the misalignment of the offset masks to improve the wafer yield.
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